1. Field of the Invention
The present invention relates to a packet command driving type memory device, particularly, to a packet command driving type memory device that can control a data output time stably and reduce an area by controlling each latency time on a long bus channel in a shift register directly.
2. Description of the Related Art
FIG. 1 shows a channel structure in a general packet command driving type memory device, for example, a memory device such as a RAMBUS DRAM. Referring to FIG. 1, a number of RAMBUS DRAMs are connected on a long bus channel, a phase difference between CTM and CFM is different every each RAMBUS DRAM. A region that a phase difference increases from a spot of xe2x80x9c0xe2x80x9d to a spot of xe2x80x9c1xe2x80x9d is referred to as a latency domain.
In a case of the longbus channel, by that a device of the latency domain being far apart from a controller reads data quickly, that the device of the latency domain being near from a controller reads data slowly, a controller can recognize data in an identical point of time from every device.
FIG. 2 shows an interface part and a shift register of a memory device for controlling a data output time according to a prior latency domain.
Referring to FIG. 2, the interface part for controlling a prior data output time comprises a first signal generating means 1 for receiving a signal SDAC less than 2:0 greater than  generated from a register 11 in the inside of a RAMBUS DRAM device and generating a signal rd5_en and a signal tDAC less than 4:1 greater than , a second signal generating means 2 for receiving a signal SRD less than 2:0 greater than  generated from the register 11 in the inside of the RAMBUS DRAM device and generating a signal rd_dly less than 2:0 greater than , a third signal generating means 3 for receiving a signal tDAC less than 4:1 greater than  generated from the first signal generating means 1 and outputting an intermediate internal signal loadRDpipe to a data output shift part, a fourth signal generating means 4 for receiving the signal tDAC less than 4:1 greater than  and the signal rd_dly less than 2:0 greater than  generated from the first and the second signal generating means 1, 2 and outputting an intermediate internal signal drainRDpipe to a data output shift part 8.
Also, the prior interface part further comprises a fifth and a sixth signal generating means 5, 6 for receiving the signal rd_dly generated from the second signal generating means 2 and outputting a signal COLLAT and a signal COLCYC to a core block 10 respectively, a seventh signal generating means 7 for receiving the signal rd_dly generated from the second signal generating means 2 and outputting a signal WriteD0123 and a signal WriteD4567 to a data input shift part 9. The signal generating means 1-7 are composed of a logic circuit.
The prior memory device having the above-mentioned structure receives a signal SDAC less than 2:0 greater than  generated from a register 11 in the inside of a device and decodes it and outputs the signal rd5_en to the data output shift part 8, outputting a signal tDAC less than 4:1 greater than  to the third and the fourth signal generating means 3, 4, the second signal generating means 2 receives a signal SRD less than 2:0 greater than  and outputs a signal rd_dly to the fourth signal generating means 4 and the fifth to the seventh signal generating means 5-7.
Accordingly, each signal generating means regulates an internal intermediate signal COLLAT, COLCYC, loadRDpipe, drainRDpipe, WriteD0123, WriteD4567 and delays an output time of read data by xe2x80x9c1t cyclexe2x80x9d.
On one hand, a signal rd5_en is inputted directly to a data output shift part 8 and causes to generate clock signals (tclk1, tclk1b), (tclk2, tclk2b) within the data output shift part 8 and control the data output shift part 8, thereby output data by delaying by xe2x80x9c1t cyclexe2x80x9d.
That is, by that the data output shift part 8 shifted data Read_Data read from the core block 10 by using a load signal loadRDpipe, drainRDpipe and a clock signal tclk, generated the internal clock signals (tclk1, tclk2) by using a signal rd5_en via a block 81 and controlled a block 82, see FIG. 3, the data output shift part 8 delayed the signal by xe2x80x9c1t cyclexe2x80x9d and compensated for an output time of data and thereby transferred data.
As described above, to compensate for an output time of data, a prior memory device generates signals rd5_en, tDAC less than 4:1 greater than , rd_dly less than 2:0 greater than  by using signals SDA less than 2:0 greater than  and SRD less than 2:0 greater than  being generated from the register 11 via each signal generating means 1-7, as drawn in FIG. 1, generates numerous control signals such as intermediate internal signals loadRDpipe, drainRDpipe, WriteD4567, COLLAT, COLCYC, etc., being subject to these signals, there was a problem that a logic composition for generating this intermediate internal signal was necessary in each signal generating means.
Also, as drawn in FIG. 2, there was a problem that a prior data output shift part 8 required a circuit receiving a signal rd_dly less than 2:0 greater than  and generating an internal clock signal, occupied a broad layout area.
And, as pulse widths of signals Write4567, loadRDpipe are made to 0.5t cycle to satisfy a data hold time as FIG. 5A to FIG. 7A, there was a problem that an operation was unstable.
This invention is invented to solve the above-mentioned prior problems, it is an object of this invention to provide a packet command driving type memory device for generating a domain signal by using a signal being generated from a register within a device and controlling a data output time directly from a shift register.
It is another object of this invention to provide a packet command driving type memory device for simplifying a logic composition of a shift register by controlling a data output time directly from a shift register by using a signal generated from a register instead of generating a control signal for controlling a shift register part in an interface part by using a signal being generated from a prior register.
It is another object of this invention to provide a packet command driving type memory device for operating stably even in a domain region which a phase difference is big by using a pulse signal having a width of xe2x80x9c1t cyclexe2x80x9d exactly.
To achieve an object of this invention, this invention comprises a first signal generating means for receiving a signal being generated from a register and generating a domain signal of certain bit; a second and a third signal generating means for generating a first and a second control signal for loading data; a fourth and a fifth signal generating means for generating a third and a fourth control signal for reading data from a core block; a data output shift part for shifting the data read from the core block according to the first and the second control signal generated from the second and a third signal generating means and a clock signal, delaying the shifted data by a certain time according to the domain signal generated from the first signal generating means according to each domain and compensating for a data output time and outputting it.
The data output shift part comprises a shift means for shifting the data read from the core block according to the first and the second control signal generated from the second and a third signal generating means and a clock signal; a data output time compensating means for delaying an output signal of the shift means by a certain time according to the domain signal generated from the first signal generating means and compensating for a data output time, outputting the compensated signal as read data via a data pad.
The data output time compensating means comprises a delay means for delaying the output signal of the shift means by a certain time according to the domain signal generated from the first signal generating means; a transfer means for transferring one of the signal delayed via the delay means or the output signal of the shift means as read data according to the domain signal generated from the first signal generating means.
And, the domain signal is 4 bits signal, the domain is divided to 5 domains.
In the data output time compensating means, the delay means comprises a number of means for delaying the output signal of the shift means by it cycle according to the domain signal.
The first delay means comprises a first transfer gate for transferring the output signal of the shift means according to a first domain signal of the domain signal generated from the first signal generating means; a first flip flop for delaying the data transferred via the first transfer gate by 1t cycle in response to the clock signal.
The second delay means comprises a second transfer gate for transferring the data delayed by 1t cycle via the first flip flop of the first delay means according to a second domain signal of the domain signal generated from the first signal generating means; a second flip flop for delaying an output of the second transfer gate by 1t cycle in response to the clock signal and outputting data delayed by 2t cycle.
The third delay means comprises a third transfer gate for transferring the data delayed by 2t cycle via the second flip flop of the second delay means according to a third domain signal of the domain signal generated from the first signal generating means; a third flip flop for delaying data transferred via the second transfer gate by 1t cycle again in response to the clock signal and outputting data delayed by 3t cycle.
The fourth delay means comprises a fourth transfer gate for transferring the signal delayed by 3t cycle via the third flip flop of the third delay means according to a fourth domain signal of the domain signal generated from the first signal generating means; a fourth flip flop for delaying data transferred via the transfer gate by 1t cycle in response to the clock signal and outputting data delayed by 4t cycle.
In the data output time compensating means, the transfer means comprises a first to a fourth transfer means for transferring the output signal of the shift means according to the domain signal generated from the first signal generating means or the signal delayed via the first to the fourth delay means of the delay means.
The first transfer means comprises a fifth transfer gate for transferring the output signal of the shift means according to a first domain signal of the domain signal generated from the first signal generating means. The second transfer means comprises a sixth transfer gate for transferring the output signal of the shift means in a first domain, an output of the first delay means in a second domain according to a second domain signal of the domain signal generated from the first signal generating means. The third transfer means comprises a seventh transfer gate for transferring an output of the sixth transfer gate in a first domain, an output of the second delay means in a third domain according to a third domain signal of the domain signal generated from the first signal generating means. The fourth transfer means comprises a eighth transfer gate for transferring an output of the seventh transfer gate in a first domain, an output of the third delay means in a third domain according to a fourth domain signal of the domain signal generated from the first signal generating means.
Also, the present invention comprises a first signal generating means for receiving a signal being generated from a register and generating a domain signal of certain bit; a second and a third signal generating means for generating a first and a second control signal for shifting data; a fourth and a fifth signal generating means for generating a third and a fourth control signal for reading data from a core block; a data output shift part having a shift means for shifting the data read from the core block according to the first and the second control signal generated from the second and a third signal generating means and a clock signal, a data output time compensating means for delaying the data shifted via the shift means by a certain time according to the domain signal generated from the first signal generating means according to each domain and compensating for a data output time and outputting the compensated signal as read data via a data pad.
The data output shift part outputs the data transferred via the shift means as read data to the data pad without a delay via the transfer means in a domain 1, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 1t cycle via a delay means and compensating for a data output time in a domain 2, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 2t cycle via a delay means and compensating for a data output time in a domain 3, outputs the data transferred via the shift means as read data to the data pad via the transfer means by delaying them by 3t cycle via a delay means and compensating for a data output time in a domain 4, outputs the data transferred via the shift means as read data to the data pad directly by delaying them by 4t cycle via a delay means and compensating for a data output time in a domain 5.